1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a pattern and method of a metal line package level test for a semiconductor device, which is capable of efficiently testing characteristic of a metal line.
2. Discussion of the Related Art
There are current, temperature, temperature gradient, and current gradient in main factors which cause electromigration (EM) in a metal line of a semiconductor device. However, taking account of only current and temperature factors, characteristic (lifetime) of the metal line in the semiconductor device is presently tested.
A background art metal line package level test pattern for a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1a and 1b are layouts of background art metal line package level test patterns for a semiconductor device.
FIG. 1a shows a JEDEC test pattern. As shown in FIG. 1a, a connecting area 3 is formed between a current applying pad 1 and a test line 2. The connecting area 3 has a width which is to be gradually narrowed toward the test line 2 so as to minimize temperature gradient and current gradient during test.
Electromigration of the metal line using the JEDEC test pattern is tested in such a manner that a current is applied to the current applying pad 1 and then a voltage of a voltage sensing area 4 at both ends of the test line 2 is measured.
In the JEDEC test pattern, the connecting area 3 is formed with a gradient to prevent temperature gradient during test. However, the JEDEC test pattern has a problem that fails to completely prevent temperature gradient by Joule heating. In addition, the JEDEC test pattern has a problem that it is likely to cause electromigration as a line width of the connecting area 3 is wider than that of the test line 2.
FIG. 1b shows a Lloyd test pattern. Referring to FIG. 1b, a connecting area 3 having a plurality of narrow lines is formed between a current applying pad 1 and a test line 2. In the same manner as FIG. 1a, the connecting area 3 has a width which is to be gradually narrowed toward the test line 2 so as to minimize temperature gradient and current gradient during test. A voltage sensing area 4 is formed at both ends of the test line 2.
Electromigration of the metal line using the Lloyd test pattern is tested in such a manner that a current is applied to the current applying pad 1 and then a voltage of the voltage sensing area 4 is measured.
In the Lloyd test pattern, the gradient connecting area 3 is formed to have the plurality of narrow lines so as to minimize temperature gradient and current gradient during test.
However, since the aforementioned background art metal line package level test patterns fail to effectively prevent temperature gradient and current gradient during the metal line test, in particular, temperature gradient by Joule heating, there exists a problem that the metal line test is not exactly performed.